The present invention relates generally to physical coding sublayer (PCS) systems and in particular the present invention relates to a scalable PCS system.
Encoding and decoding systems are often used in data communication. For example, fiber optic systems often use a byte oriented DC balanced run length limited 8B/10B encoder/decoder. One example of an 8B/10B encoder is provided in U.S. Pat. No. 4,486,739 issued Dec. 4, 1984 for xe2x80x9cByte Oriented DC Balanced 8B/10B Partitioned Block Transmission Codexe2x80x9d by Franaszek et al., incorporated herein by reference. The Franaszek 8B/10B encoder/decoder partitions an 8-bit input word into a 5-bit portion and a 3-bit portion. The 5-bit portion is encoded into a 6-bit output, and the 3-bit portion is encoded into a 4-bit output. A detailed description of an 8B/10B encoding technique is described in Franaszek.
Run length is defined as a number of identical contiguous symbols (ones or zeros) that appear in a data stream. A large number of contiguous binary ones will produce a highly positive DC signal, whereas a large number of contiguous binary zeros will produce a highly negative DC signal. It is important, however, to maintain a DC balanced in the signal, both in long data strings as well as short data strings.
A disparity of a block of data is the difference between a number of data one bits and a number of data zero bits in a block of data. The Franaszek patent adjusts a DC level on output data by comparing the running disparity from prior words to the disparity of a current word being encoded. The output data word, or a complement thereof, is then output based upon the comparison. For example, if the running disparity is +1 and the current output word has a disparity of +2, the current output data is complemented to a word with a disparity of xe2x88x922 and a xe2x88x921 disparity is internally passed to the next encoding stage. That is, the running disparity from a 5B/6B encoder stage is passed to a 3B/4B encoder stage, and the running disparity from the 3B/4B encoder stage is held to encode the 5-bit input portion of the next word in the 5B/6B encoder. The running disparity for the 5B/6B encoder is latched on the negative edge of the clock, and coupled to the 3B/4B encoder. Similarly, the output of the running disparity from the 3B/4B encoder is latched on the positive edge of the clock and coupled to the 5B/6B block.
Bandwidth requirements of transmitted data are increasing with the increase in communication speeds. For example, the above-described encoder can handle a single 1.25 Gbit data channel. However, a 6.25 Gbit channel may be desired. Present 8B/10B encoders are not scalable to provide these increased bandwidth requirements.
A 16B/20B encoder is described in U.S. Pat. No. 5,663,724 entitled xe2x80x9c16B/20B Encoderxe2x80x9d to Westby, issued Sep. 2, 1997, incorporated herein by reference. The described encoder includes upper 5B/6B and 3B/4B encoder blocks and lower 5B/6B and 3B/4B encoder blocks. The single device couples a disparity from the upper 5B/6B block to the upper 3B/4B encoder block. A disparity from the upper 3B/4B encoder block is coupled to the lower 5B/6B encoder block. Likewise, a disparity from the lower 5B/6B block is coupled to the lower 3B/4B encoder block, and disparity from the lower 3B/4B encoder block is coupled to the upper 5B/6B encoder block. The described 16B/20B encoder is not scalable and a disparity of the upper 10 bits may not be accurately reflected in the lower 10 bits.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a scalable physical coding sublayer. There is a further need for a scalable 8B/10B encoder/decoder.
The above-mentioned problems with encoders/decoders and other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention provides a scalable 8B/10B encoder/decoder.
In one embodiment, a scalable physical coding sublayer (PCS) system comprises N-encoders to receive input data, each of the N-encoders provides encoded X-bit output data, and a controller to operate the N encoders to provide from 1 to N channels, along with combinations of integer multiples, Y, of the single channel, whose sum does not exceed N, each channel providing Y*X output bits, with the combined channel structure outputting X*N bits.
In another embodiment, a scalable physical coding sublayer (PCS) system comprises N-encoders to receive input data and provide encoded output data. Each of the N-encoders have synchronous and asynchronous data disparity outputs and defines a single communication channel. Disparity select circuitry is coupled to the N-encoders, and a controller is provided to operate the disparity select circuitry to provide an N-wide communication channel.
In yet another embodiment, a physical coding sublayer (PCS) system comprises a state machine, an eight-bit input to receive eight bits of input data, and an eight-bit to ten-bit encoder coupled to the state machine and the eight-bit input. The eight-bit to ten-bit encoder comprises encoder circuitry to encode the eight bits of input data into ten bits of output data, disparity control circuitry to calculate a running disparity of the ten bits of output data, an output disparity connection to provide the running disparity of the ten bits of output data, and an input disparity connection to receive an externally provided running disparity.
An 8B/10B encoder comprises eight input data connections to receive eight input data signals, a control input connection to receive a control signal, a disparity input connection to receive a disparity input signal, and ten output data connections to provide ten encoded output data signals. A disparity output connection is provided to indicate a running disparity based on the ten encoded output data signals and the disparity input signal.